There are countless applications for memory devices capable of storing in a nonvolatile manner large quantities of data to be saved or made accessible in a successive time by a processor, such as for instance memory devices for PCBios applications coupled to a PCI bus, in digital cameras, electronic agendas, measuring instruments, electronic equipment of vehicles and the like.
Nowadays, the memory devices most frequently used in these applications are the so-called FLASH memories.
Data may be written in the memory and read from it, making the data available through an interface circuit.
A standard FLASH memory device embodies address circuitry, row and column decoding circuits, data read and write circuits, controlled by a memory controller, often in the form of a microcontroller integrated in the same device. The functioning mode of a standard FLASH memory device is parallel through a control and input/output bus whose lines are connected to as many pins of the device.
The controller of a FLASH memory device coordinates the recording of the information acquired in specific locations of the memory cell array from which data may be successively read and made available to the external circuitry.
Of course, the memory controller performs all functions necessary to ensure a correct functioning of the device, by establishing redundancy or by-pass functions of locations of defective cells during the read and write cycles.
Often these FLASH memory devices include also a serial interface designed for implementing or supporting a certain serial communication protocol that determines, by using a clock signal, the execution of the distinct steps of the communication protocol, both during a data read phase and a data write phase.
Very often the serial communication protocol is of the type known as LPC (acronym for Low Pin Count).
In many applications, the parallel mode is used during the testing on wafer (EWS) of the device being fabricated and eventually for accelerating the writing of a large quantity of data to be written in the memory in a substantially permanent fashion.
For a chip manufacturer, the compatibility of a certain nonvolatile memory device with the different (or potentially different) requisites of its customers—typically manufacturers of electronic equipment—has a great importance.
The possibility of making a mass production memory device compatible with a specific serial communication protocol according to the requirements of a customer in a “final” sequence of steps of the fabrication process produces a non negligible economy of scale, because of the possibility of fabricating devices in augmented quantities for satisfying the needs of a number of customers.
The advantage of producing a device whose serial communication protocol could be selected by establishing a certain logic state on a pin of the device itself would be even more significant, because the user would have the possibility of choosing among different serial communication protocols by conditioning the same finished product.
On another side, in these kinds of devices, the available number of pins remains a relatively critical design aspect and it is generally difficult to render available pins for implementing other functions beside those more directly correlated to the functions of an already complex memory device. Moreover, the integration of additional circuit blocks destined to the execution of alternatively selectable functions such as would be the case of selectable multiple serial interfaces, each dedicated to implement a certain communication protocol, implies problematic costs/benefit consideration for devices in which a large memory capacity is favored when dimensions and the packaging of the device are pre-established.